judsonupchurch/nanoMODBUS
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

refined stm32 example to pass clang format checker

Browse Source
This commit is contained in:
Donghoon Park 2024-12-15 03:17:00 +00:00
parent 9b57f7697f
commit 3c23889d47
3 changed files with 442 additions and 379 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
examples/stm32/FreeRTOSConfig.h
View File

@ -2,22 +2,23 @@
* FreeRTOS Kernel V10.4.1
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
@ -25,7 +26,6 @@
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
@ -137,14 +137,21 @@ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configKERNEL_INTERRUPT_PRIORITY \
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define configASSERT(x) \
if ((x) == 0) { \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */

140
examples/stm32/bsp/blackpill/blackpill.c
View File

@ -3,19 +3,26 @@
*
* 1. System Clock Configuration:
* - External high-speed oscillator (HSE) enabled.
* - PLL is configured with source from HSE, PLLM = 25, PLLN = 336, PLLP = 4, PLLQ = 7.
* - PLL is configured with source from HSE, PLLM = 25, PLLN = 336, PLLP = 4,
* PLLQ = 7.
* - System clock (SYSCLK) sourced from PLL output at 84 MHz.
* - AHB clock (HCLK) running at SYSCLK.
* - APB1 clock (PCLK1) running at HCLK / 2 (42 MHz).
* - APB2 clock (PCLK2) running at HCLK.
*
* 2. GPIO Configuration:
* - GPIOC Pin 13: Configured as output (Push Pull), used for LED control, low frequency.
* - GPIOB Pin 7: Configured as input, no pull-up/pull-down, used as input for interrupts.
* - GPIOB Pin 6: Configured as open-drain output, low frequency, initially set high.
* - GPIOA Pin 15: Configured as output (Push Pull), used for NSS in SPI1 communication, very high frequency.
* - GPIOA Pins 9 (TX), 10 (RX): Configured as alternate function (AF7) for USART1 communication.
* - GPIOB Pins 3 (SCLK), 4 (MISO), 5 (MOSI): Configured as alternate function (AF5) for SPI1 communication.
* - GPIOC Pin 13: Configured as output (Push Pull), used for LED control,
* low frequency.
* - GPIOB Pin 7: Configured as input, no pull-up/pull-down, used as input
* for interrupts.
* - GPIOB Pin 6: Configured as open-drain output, low frequency, initially
* set high.
* - GPIOA Pin 15: Configured as output (Push Pull), used for NSS in SPI1
* communication, very high frequency.
* - GPIOA Pins 9 (TX), 10 (RX): Configured as alternate function (AF7) for
* USART1 communication.
* - GPIOB Pins 3 (SCLK), 4 (MISO), 5 (MOSI): Configured as alternate
* function (AF5) for SPI1 communication.
*
* 3. SPI1 Configuration:
* - Mode: Master.
@ -28,7 +35,8 @@
* - First Bit: MSB.
* - TI Mode: Disabled.
* - CRC Calculation: Disabled.
* - Pins: PB3 (SCLK), PB4 (MISO), PB5 (MOSI) configured as alternate function.
* - Pins: PB3 (SCLK), PB4 (MISO), PB5 (MOSI) configured as alternate
* function.
*
* 4. USART1 Configuration:
* - Baud Rate: 115200.
@ -41,20 +49,28 @@
* - Pins: PA9 (TX), PA10 (RX) configured as alternate function.
*
* 5. DMA Configuration:
* - DMA2_Stream3 (SPI1_TX): Used for SPI1 TX, configured for memory-to-peripheral, channel 3.
* - Memory increment enabled, peripheral increment disabled, normal mode, low priority.
* - DMA2_Stream3 (SPI1_TX): Used for SPI1 TX, configured for
* memory-to-peripheral, channel 3.
* - Memory increment enabled, peripheral increment disabled, normal mode,
* low priority.
* - Linked to SPI1_TX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
* - DMA2_Stream0 (SPI1_RX): Used for SPI1 RX, configured for peripheral-to-memory, channel 3.
* - Memory increment enabled, peripheral increment disabled, normal mode, high priority.
* - DMA2_Stream0 (SPI1_RX): Used for SPI1 RX, configured for
* peripheral-to-memory, channel 3.
* - Memory increment enabled, peripheral increment disabled, normal mode,
* high priority.
* - Linked to SPI1_RX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
* - DMA2_Stream7 (USART1_TX): Used for USART1 TX, configured for memory-to-peripheral, channel 4.
* - Memory increment enabled, peripheral increment disabled, normal mode, low priority.
* - DMA2_Stream7 (USART1_TX): Used for USART1 TX, configured for
* memory-to-peripheral, channel 4.
* - Memory increment enabled, peripheral increment disabled, normal mode,
* low priority.
* - Linked to USART1_TX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
* - DMA2_Stream2 (USART1_RX): Used for USART1 RX, configured for peripheral-to-memory, channel 4.
* - Memory increment enabled, peripheral increment disabled, normal mode, high priority.
* - DMA2_Stream2 (USART1_RX): Used for USART1 RX, configured for
* peripheral-to-memory, channel 4.
* - Memory increment enabled, peripheral increment disabled, normal mode,
* high priority.
* - Linked to USART1_RX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
*
@ -65,11 +81,13 @@
* - DMA2 clock enabled for DMA streams (used for SPI1 and USART1).
*
* 7. Interrupt Configuration:
* - DMA2_Stream3 (SPI1_TX), DMA2_Stream0 (SPI1_RX), DMA2_Stream7 (USART1_TX), DMA2_Stream2 (USART1_RX).
* - DMA2_Stream3 (SPI1_TX), DMA2_Stream0 (SPI1_RX), DMA2_Stream7
* (USART1_TX), DMA2_Stream2 (USART1_RX).
* - All configured with priority level 0 and interrupts enabled.
*
* 8. Error Handling:
* - Error_Handler function enters an infinite loop to indicate an error state.
* - Error_Handler function enters an infinite loop to indicate an error
* state.
*/
#include "blackpill/blackpill.h"
@ -90,8 +108,7 @@ UART_HandleTypeDef huart1;
DMA_HandleTypeDef hdma_usart1_tx;
DMA_HandleTypeDef hdma_usart1_rx;
void BSP_Init(void)
{
void BSP_Init(void) {
// Initialize the HAL Library
HAL_Init();
@ -105,8 +122,7 @@ void BSP_Init(void)
MX_USART1_UART_Init();
}
void SystemClock_Config(void)
{
void SystemClock_Config(void) {
// System Clock Configuration Code
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
@ -123,8 +139,8 @@ void SystemClock_Config(void)
HAL_RCC_OscConfig(&RCC_OscInitStruct);
// Initialize the CPU, AHB, and APB buses clocks
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
@ -132,8 +148,7 @@ void SystemClock_Config(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
}
static void MX_GPIO_Init(void)
{
static void MX_GPIO_Init(void) {
GPIO_InitTypeDef GPIO_InitStruct = {0};
// Enable GPIOC clock
@ -174,8 +189,7 @@ static void MX_GPIO_Init(void)
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
static void MX_USART1_UART_Init(void)
{
static void MX_USART1_UART_Init(void) {
// USART1 initialization settings
__HAL_RCC_USART1_CLK_ENABLE();
@ -188,8 +202,7 @@ static void MX_USART1_UART_Init(void)
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
if (HAL_UART_Init(&huart1) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -205,19 +218,17 @@ static void MX_USART1_UART_Init(void)
// Enable GPIOA clock
__HAL_RCC_GPIOA_CLK_ENABLE();
// Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push Pull
// Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push
// Pull
GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
static void MX_SPI1_Init(void)
{
static void MX_SPI1_Init(void) {
__HAL_RCC_SPI1_CLK_ENABLE();
// SPI1 initialization settings
hspi1.Instance = SPI1;
@ -225,16 +236,18 @@ static void MX_SPI1_Init(void)
hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
hspi1.Init.CLKPhase =
SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
hspi1.Init.BaudRatePrescaler =
SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
hspi1.Init.CRCCalculation =
SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
if (HAL_SPI_Init(&hspi1) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -252,11 +265,9 @@ static void MX_SPI1_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
static void MX_DMA_Init(void)
{
static void MX_DMA_Init(void) {
// DMA controller clock enable
__HAL_RCC_DMA2_CLK_ENABLE();
@ -271,8 +282,7 @@ static void MX_DMA_Init(void)
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
{
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -290,8 +300,7 @@ static void MX_DMA_Init(void)
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
{
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -309,8 +318,7 @@ static void MX_DMA_Init(void)
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
{
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -329,8 +337,7 @@ static void MX_DMA_Init(void)
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
{
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@ -354,33 +361,18 @@ static void MX_DMA_Init(void)
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
}
void Error_Handler(void)
{
void Error_Handler(void) {
// If an error occurs, stay in infinite loop
while(1) {}
while (1) {
}
}
void DMA2_Stream3_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_spi1_tx);
}
void DMA2_Stream3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); }
void DMA2_Stream0_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_spi1_rx);
}
void DMA2_Stream0_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); }
void DMA2_Stream7_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_usart1_tx);
}
void DMA2_Stream7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_tx); }
void DMA2_Stream2_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_usart1_rx);
}
void DMA2_Stream2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_rx); }
void USART1_IRQHandler(void)
{
HAL_UART_IRQHandler(&huart1);
}
void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&huart1); }

216
examples/stm32/stm32f4xx_hal_conf.h
View File

@ -86,9 +86,10 @@
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
* @brief Adjust the value of External High Speed oscillator (HSE) used in your
* application. This value is used by the RCC HAL module to compute the system
* frequency (when HSE is used as system clock source, directly or through the
* PLL).
*/
#if !defined(HSE_VALUE)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
@ -100,8 +101,9 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
* This value is used by the RCC HAL module to compute the system
* frequency (when HSI is used as system clock source, directly or through the
* PLL).
*/
#if !defined(HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
@ -112,14 +114,15 @@
*/
#if !defined(LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz \
The real value may vary depending on the \
variations in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined(LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#define LSE_VALUE \
32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined(LSE_STARTUP_TIMEOUT)
@ -128,11 +131,12 @@
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* This value is used by the I2S HAL module to compute the I2S clock
* source frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined(EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
#define EXTERNAL_CLOCK_VALUE \
12288000U /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -149,44 +153,82 @@
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_ADC_REGISTER_CALLBACKS \
0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS \
0U /* CAN register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS \
0U /* CEC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS \
0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS \
0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS \
0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS \
0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS \
0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS \
0U /* DSI register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS \
0U /* ETH register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS \
0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS \
0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS \
0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS \
0U /* FMPI2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS \
0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS \
0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS \
0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS \
0U /* LTDC register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS \
0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS \
0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS \
0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS \
0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS \
0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS \
0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS \
0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS \
0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS \
0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS \
0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS \
0U /* SMARTCARD register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS \
0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS \
0U /* SRAM register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS \
0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS \
0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS \
0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS \
0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS \
0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS \
0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS \
0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */
/**
@ -208,8 +250,10 @@
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RX_BUF_SIZE \
ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE \
ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
@ -232,34 +276,55 @@
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_FULLDUPLEX_100M \
((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M \
((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M \
((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M \
((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION \
((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION \
((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN \
((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE \
((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
#define PHY_AUTONEGO_COMPLETE \
((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS \
((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION \
((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_SR \
((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR \
((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR \
((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_LINK_STATUS \
((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS \
((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS \
((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MICR_INT_EN \
((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE \
((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
#define PHY_MISR_LINK_INT_EN \
((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT \
((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
@ -477,19 +542,18 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) \
((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/