diff --git a/examples/stm32/FreeRTOSConfig.h b/examples/stm32/FreeRTOSConfig.h
index 8d41cbc..70c6841 100644
--- a/examples/stm32/FreeRTOSConfig.h
+++ b/examples/stm32/FreeRTOSConfig.h
@@ -2,22 +2,23 @@
* FreeRTOS Kernel V10.4.1
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
@@ -25,7 +26,6 @@
* 1 tab == 4 spaces!
*/
-
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
@@ -45,57 +45,57 @@
extern uint32_t SystemCoreClock;
#if defined STM32L5
- #define configENABLE_TRUSTZONE 0
- #if configENABLE_TRUSTZONE
- #define configMINIMAL_SECURE_STACK_SIZE ((uint16_t)1024)
- #endif
- #define configRUN_FREERTOS_SECURE_ONLY 0
- #define configENABLE_FPU 1
- #define configENABLE_MPU 0
+#define configENABLE_TRUSTZONE 0
+#if configENABLE_TRUSTZONE
+#define configMINIMAL_SECURE_STACK_SIZE ((uint16_t)1024)
+#endif
+#define configRUN_FREERTOS_SECURE_ONLY 0
+#define configENABLE_FPU 1
+#define configENABLE_MPU 0
#endif
-#define configUSE_PREEMPTION 1
-#define configUSE_IDLE_HOOK 0
-#define configUSE_TICK_HOOK 0
-#define configCPU_CLOCK_HZ ( SystemCoreClock )
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)1000)
#if !defined USE_CMSIS_RTOS_V2
-#define configMAX_PRIORITIES ( 5 )
+#define configMAX_PRIORITIES (5)
#endif
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 50 )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) )
-#define configMAX_TASK_NAME_LEN ( 10 )
-#define configUSE_TRACE_FACILITY 1
-#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_MUTEXES 1
-#define configQUEUE_REGISTRY_SIZE 8
-#define configCHECK_FOR_STACK_OVERFLOW 0
-#define configUSE_RECURSIVE_MUTEXES 1
-#define configUSE_MALLOC_FAILED_HOOK 0
-#define configUSE_APPLICATION_TASK_TAG 0
-#define configUSE_COUNTING_SEMAPHORES 1
-#define configGENERATE_RUN_TIME_STATS 0
+#define configMINIMAL_STACK_SIZE ((unsigned short)50)
+#define configTOTAL_HEAP_SIZE ((size_t)(32 * 1024))
+#define configMAX_TASK_NAME_LEN (10)
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
/* Software timer definitions. */
-#define configUSE_TIMERS 1
-#define configTIMER_TASK_PRIORITY ( 2 )
-#define configTIMER_QUEUE_LENGTH 10
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (2)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 1
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
#if defined USE_CMSIS_RTOS_V2
@@ -119,33 +119,40 @@ to exclude the API function. */
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
- /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
- #define configPRIO_BITS __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
#else
- #define configPRIO_BITS 4 /* 15 priority levels */
+#define configPRIO_BITS 4 /* 15 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+#define configKERNEL_INTERRUPT_PRIORITY \
+ (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
+ (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
-
+#define configASSERT(x) \
+ if ((x) == 0) { \
+ taskDISABLE_INTERRUPTS(); \
+ for (;;) \
+ ; \
+ }
+
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
diff --git a/examples/stm32/bsp/blackpill/blackpill.c b/examples/stm32/bsp/blackpill/blackpill.c
index e727dc8..25402db 100644
--- a/examples/stm32/bsp/blackpill/blackpill.c
+++ b/examples/stm32/bsp/blackpill/blackpill.c
@@ -1,21 +1,28 @@
/*
* STM32F401CCU6 Board Support Package (BSP) Summary:
- *
+ *
* 1. System Clock Configuration:
* - External high-speed oscillator (HSE) enabled.
- * - PLL is configured with source from HSE, PLLM = 25, PLLN = 336, PLLP = 4, PLLQ = 7.
+ * - PLL is configured with source from HSE, PLLM = 25, PLLN = 336, PLLP = 4,
+ * PLLQ = 7.
* - System clock (SYSCLK) sourced from PLL output at 84 MHz.
* - AHB clock (HCLK) running at SYSCLK.
* - APB1 clock (PCLK1) running at HCLK / 2 (42 MHz).
* - APB2 clock (PCLK2) running at HCLK.
*
* 2. GPIO Configuration:
- * - GPIOC Pin 13: Configured as output (Push Pull), used for LED control, low frequency.
- * - GPIOB Pin 7: Configured as input, no pull-up/pull-down, used as input for interrupts.
- * - GPIOB Pin 6: Configured as open-drain output, low frequency, initially set high.
- * - GPIOA Pin 15: Configured as output (Push Pull), used for NSS in SPI1 communication, very high frequency.
- * - GPIOA Pins 9 (TX), 10 (RX): Configured as alternate function (AF7) for USART1 communication.
- * - GPIOB Pins 3 (SCLK), 4 (MISO), 5 (MOSI): Configured as alternate function (AF5) for SPI1 communication.
+ * - GPIOC Pin 13: Configured as output (Push Pull), used for LED control,
+ * low frequency.
+ * - GPIOB Pin 7: Configured as input, no pull-up/pull-down, used as input
+ * for interrupts.
+ * - GPIOB Pin 6: Configured as open-drain output, low frequency, initially
+ * set high.
+ * - GPIOA Pin 15: Configured as output (Push Pull), used for NSS in SPI1
+ * communication, very high frequency.
+ * - GPIOA Pins 9 (TX), 10 (RX): Configured as alternate function (AF7) for
+ * USART1 communication.
+ * - GPIOB Pins 3 (SCLK), 4 (MISO), 5 (MOSI): Configured as alternate
+ * function (AF5) for SPI1 communication.
*
* 3. SPI1 Configuration:
* - Mode: Master.
@@ -28,7 +35,8 @@
* - First Bit: MSB.
* - TI Mode: Disabled.
* - CRC Calculation: Disabled.
- * - Pins: PB3 (SCLK), PB4 (MISO), PB5 (MOSI) configured as alternate function.
+ * - Pins: PB3 (SCLK), PB4 (MISO), PB5 (MOSI) configured as alternate
+ * function.
*
* 4. USART1 Configuration:
* - Baud Rate: 115200.
@@ -41,20 +49,28 @@
* - Pins: PA9 (TX), PA10 (RX) configured as alternate function.
*
* 5. DMA Configuration:
- * - DMA2_Stream3 (SPI1_TX): Used for SPI1 TX, configured for memory-to-peripheral, channel 3.
- * - Memory increment enabled, peripheral increment disabled, normal mode, low priority.
+ * - DMA2_Stream3 (SPI1_TX): Used for SPI1 TX, configured for
+ * memory-to-peripheral, channel 3.
+ * - Memory increment enabled, peripheral increment disabled, normal mode,
+ * low priority.
* - Linked to SPI1_TX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
- * - DMA2_Stream0 (SPI1_RX): Used for SPI1 RX, configured for peripheral-to-memory, channel 3.
- * - Memory increment enabled, peripheral increment disabled, normal mode, high priority.
+ * - DMA2_Stream0 (SPI1_RX): Used for SPI1 RX, configured for
+ * peripheral-to-memory, channel 3.
+ * - Memory increment enabled, peripheral increment disabled, normal mode,
+ * high priority.
* - Linked to SPI1_RX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
- * - DMA2_Stream7 (USART1_TX): Used for USART1 TX, configured for memory-to-peripheral, channel 4.
- * - Memory increment enabled, peripheral increment disabled, normal mode, low priority.
+ * - DMA2_Stream7 (USART1_TX): Used for USART1 TX, configured for
+ * memory-to-peripheral, channel 4.
+ * - Memory increment enabled, peripheral increment disabled, normal mode,
+ * low priority.
* - Linked to USART1_TX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
- * - DMA2_Stream2 (USART1_RX): Used for USART1 RX, configured for peripheral-to-memory, channel 4.
- * - Memory increment enabled, peripheral increment disabled, normal mode, high priority.
+ * - DMA2_Stream2 (USART1_RX): Used for USART1 RX, configured for
+ * peripheral-to-memory, channel 4.
+ * - Memory increment enabled, peripheral increment disabled, normal mode,
+ * high priority.
* - Linked to USART1_RX using __HAL_LINKDMA.
* - Interrupt priority level 0, enabled.
*
@@ -65,11 +81,13 @@
* - DMA2 clock enabled for DMA streams (used for SPI1 and USART1).
*
* 7. Interrupt Configuration:
- * - DMA2_Stream3 (SPI1_TX), DMA2_Stream0 (SPI1_RX), DMA2_Stream7 (USART1_TX), DMA2_Stream2 (USART1_RX).
+ * - DMA2_Stream3 (SPI1_TX), DMA2_Stream0 (SPI1_RX), DMA2_Stream7
+ * (USART1_TX), DMA2_Stream2 (USART1_RX).
* - All configured with priority level 0 and interrupts enabled.
*
* 8. Error Handling:
- * - Error_Handler function enters an infinite loop to indicate an error state.
+ * - Error_Handler function enters an infinite loop to indicate an error
+ * state.
*/
#include "blackpill/blackpill.h"
@@ -90,8 +108,7 @@ UART_HandleTypeDef huart1;
DMA_HandleTypeDef hdma_usart1_tx;
DMA_HandleTypeDef hdma_usart1_rx;
-void BSP_Init(void)
-{
+void BSP_Init(void) {
// Initialize the HAL Library
HAL_Init();
@@ -105,8 +122,7 @@ void BSP_Init(void)
MX_USART1_UART_Init();
}
-void SystemClock_Config(void)
-{
+void SystemClock_Config(void) {
// System Clock Configuration Code
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
@@ -123,8 +139,8 @@ void SystemClock_Config(void)
HAL_RCC_OscConfig(&RCC_OscInitStruct);
// Initialize the CPU, AHB, and APB buses clocks
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
@@ -132,8 +148,7 @@ void SystemClock_Config(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
}
-static void MX_GPIO_Init(void)
-{
+static void MX_GPIO_Init(void) {
GPIO_InitTypeDef GPIO_InitStruct = {0};
// Enable GPIOC clock
@@ -155,7 +170,7 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- // Configure GPIOB Pin 6 as output with Open Drain mode
+ // Configure GPIOB Pin 6 as output with Open Drain mode
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -174,8 +189,7 @@ static void MX_GPIO_Init(void)
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
-static void MX_USART1_UART_Init(void)
-{
+static void MX_USART1_UART_Init(void) {
// USART1 initialization settings
__HAL_RCC_USART1_CLK_ENABLE();
@@ -188,8 +202,7 @@ static void MX_USART1_UART_Init(void)
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
- if (HAL_UART_Init(&huart1) != HAL_OK)
- {
+ if (HAL_UART_Init(&huart1) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@@ -198,43 +211,43 @@ static void MX_USART1_UART_Init(void)
// It must higher or equal than 5
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
-
+
// USART1 Pin configuration: TX (PA9), RX (PA10)
GPIO_InitTypeDef GPIO_InitStruct = {0};
// Enable GPIOA clock
__HAL_RCC_GPIOA_CLK_ENABLE();
- // Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push Pull
+ // Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push
+ // Pull
GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-
}
-static void MX_SPI1_Init(void)
-{
+static void MX_SPI1_Init(void) {
__HAL_RCC_SPI1_CLK_ENABLE();
// SPI1 initialization settings
hspi1.Instance = SPI1;
- hspi1.Init.Mode = SPI_MODE_MASTER; // Set SPI1 as master
- hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
- hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
- hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
- hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
- hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
- hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
- hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
- hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
- hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
+ hspi1.Init.Mode = SPI_MODE_MASTER; // Set SPI1 as master
+ hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
+ hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
+ hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
+ hspi1.Init.CLKPhase =
+ SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
+ hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
+ hspi1.Init.BaudRatePrescaler =
+ SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
+ hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
+ hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
+ hspi1.Init.CRCCalculation =
+ SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
-
- if (HAL_SPI_Init(&hspi1) != HAL_OK)
- {
+
+ if (HAL_SPI_Init(&hspi1) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@@ -252,11 +265,9 @@ static void MX_SPI1_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
}
-static void MX_DMA_Init(void)
-{
+static void MX_DMA_Init(void) {
// DMA controller clock enable
__HAL_RCC_DMA2_CLK_ENABLE();
@@ -271,8 +282,7 @@ static void MX_DMA_Init(void)
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
- {
+ if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@@ -290,8 +300,7 @@ static void MX_DMA_Init(void)
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
- {
+ if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@@ -309,8 +318,7 @@ static void MX_DMA_Init(void)
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
- {
+ if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
@@ -329,15 +337,14 @@ static void MX_DMA_Init(void)
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
- {
+ if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) {
// Initialization error handling
Error_Handler();
}
__HAL_LINKDMA(&huart1, hdmarx, hdma_usart1_rx);
- // DMA2_Stream3 (SPI1_TX) Interrupt Configuration
+ // DMA2_Stream3 (SPI1_TX) Interrupt Configuration
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
@@ -354,33 +361,18 @@ static void MX_DMA_Init(void)
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
}
-void Error_Handler(void)
-{
+void Error_Handler(void) {
// If an error occurs, stay in infinite loop
- while(1) {}
+ while (1) {
+ }
}
-void DMA2_Stream3_IRQHandler(void)
-{
- HAL_DMA_IRQHandler(&hdma_spi1_tx);
-}
+void DMA2_Stream3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); }
-void DMA2_Stream0_IRQHandler(void)
-{
- HAL_DMA_IRQHandler(&hdma_spi1_rx);
-}
+void DMA2_Stream0_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); }
-void DMA2_Stream7_IRQHandler(void)
-{
- HAL_DMA_IRQHandler(&hdma_usart1_tx);
-}
+void DMA2_Stream7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_tx); }
-void DMA2_Stream2_IRQHandler(void)
-{
- HAL_DMA_IRQHandler(&hdma_usart1_rx);
-}
+void DMA2_Stream2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_rx); }
-void USART1_IRQHandler(void)
-{
- HAL_UART_IRQHandler(&huart1);
-}
+void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&huart1); }
diff --git a/examples/stm32/stm32f4xx_hal_conf.h b/examples/stm32/stm32f4xx_hal_conf.h
index a123547..bf7e9f1 100644
--- a/examples/stm32/stm32f4xx_hal_conf.h
+++ b/examples/stm32/stm32f4xx_hal_conf.h
@@ -1,30 +1,30 @@
/**
- ******************************************************************************
- * @file stm32f4xx_hal_conf_template.h
- * @author MCD Application Team
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32f4xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
@@ -32,9 +32,9 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
// #define HAL_ADC_MODULE_ENABLED
// #define HAL_CAN_MODULE_ENABLED
// #define HAL_CAN_LEGACY_MODULE_ENABLED
@@ -86,113 +86,155 @@
/* ########################## HSE/HSI Values adaptation ##################### */
/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your
+ * application. This value is used by the RCC HAL module to compute the system
+ * frequency (when HSE is used as system clock source, directly or through the
+ * PLL).
+ */
+#if !defined(HSE_VALUE)
+#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
+#if !defined(HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
-#endif /* HSI_VALUE */
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system
+ * frequency (when HSI is used as system clock source, directly or through the
+ * PLL).
+ */
+#if !defined(HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined(LSI_VALUE)
+#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz \
+ The real value may vary depending on the \
+ variations in voltage and temperature. */
/**
- * @brief External Low Speed oscillator (LSE) value.
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined(LSE_VALUE)
+#define LSE_VALUE \
+ 32768U /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
+#if !defined(LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock
+ * source frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined(EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE \
+ 12288000U /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
-#define INSTRUCTION_CACHE_ENABLE 1U
-#define DATA_CACHE_ENABLE 1U
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
-#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
-#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
-#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
-#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
-#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
-#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
-#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
-#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
-#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
-#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
-#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
-#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
-#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
-#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
-#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
-#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
-#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
-#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
-#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
-#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
-#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
-#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
-#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
-#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
-#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
-#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
-#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
-#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
-#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
-#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
-#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
-#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
-#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
-#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
-#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
-#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+#define USE_HAL_ADC_REGISTER_CALLBACKS \
+ 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS \
+ 0U /* CAN register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS \
+ 0U /* CEC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS \
+ 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS \
+ 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS \
+ 0U /* DCMI register callback disabled */
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS \
+ 0U /* DFSDM register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS \
+ 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS \
+ 0U /* DSI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS \
+ 0U /* ETH register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS \
+ 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS \
+ 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS \
+ 0U /* I2C register callback disabled */
+#define USE_HAL_FMPI2C_REGISTER_CALLBACKS \
+ 0U /* FMPI2C register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS \
+ 0U /* I2S register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS \
+ 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS \
+ 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS \
+ 0U /* LTDC register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS \
+ 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS \
+ 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS \
+ 0U /* NOR register callback disabled */
+#define USE_HAL_PCCARD_REGISTER_CALLBACKS \
+ 0U /* PCCARD register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS \
+ 0U /* PCD register callback disabled */
+#define USE_HAL_QSPI_REGISTER_CALLBACKS \
+ 0U /* QSPI register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS \
+ 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS \
+ 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS \
+ 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS \
+ 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS \
+ 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS \
+ 0U /* SDRAM register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS \
+ 0U /* SRAM register callback disabled */
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS \
+ 0U /* SPDIFRX register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS \
+ 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS \
+ 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS \
+ 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS \
+ 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS \
+ 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS \
+ 0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
@@ -200,296 +242,318 @@
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2U
-#define MAC_ADDR1 0U
-#define MAC_ADDR2 0U
-#define MAC_ADDR3 0U
-#define MAC_ADDR4 0U
-#define MAC_ADDR5 0U
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE \
+ ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE \
+ ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY 0x000000FFU
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY 0x00000FFFU
+#define PHY_CONFIG_DELAY 0x00000FFFU
-#define PHY_READ_TO 0x0000FFFFU
-#define PHY_WRITE_TO 0x0000FFFFU
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
-#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M \
+ ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M \
+ ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M \
+ ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M \
+ ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION \
+ ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION \
+ ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN \
+ ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE \
+ ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE \
+ ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS \
+ ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION \
+ ((uint16_t)0x0002) /*!< Jabber condition detected */
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
-#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+#define PHY_SR \
+ ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR \
+ ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR \
+ ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
-#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
-#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+#define PHY_LINK_STATUS \
+ ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS \
+ ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS \
+ ((uint16_t)0x0004) /*!< PHY Duplex mask */
-#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
-#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+#define PHY_MICR_INT_EN \
+ ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE \
+ ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN \
+ ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT \
+ ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
-#define USE_SPI_CRC 1U
+#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
- */
+ * @brief Include module's header file
+ */
#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f4xx_hal_rcc.h"
+#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f4xx_hal_gpio.h"
+#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32f4xx_hal_exti.h"
+#include "stm32f4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32f4xx_hal_dma.h"
+#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f4xx_hal_cortex.h"
+#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f4xx_hal_adc.h"
+#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f4xx_hal_can.h"
+#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "stm32f4xx_hal_can_legacy.h"
+#include "stm32f4xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f4xx_hal_crc.h"
+#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32f4xx_hal_cryp.h"
+#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
- #include "stm32f4xx_hal_dma2d.h"
+#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f4xx_hal_dac.h"
+#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32f4xx_hal_dcmi.h"
+#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
- #include "stm32f4xx_hal_eth.h"
+#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f4xx_hal_flash.h"
+#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
-
+
#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f4xx_hal_sram.h"
+#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f4xx_hal_nor.h"
+#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f4xx_hal_nand.h"
+#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
+#include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32f4xx_hal_sdram.h"
+#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
+#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
+#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
+#include "stm32f4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
+#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
+#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
+#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
+#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
+#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
+#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
+#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
+#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
+#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
+#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
+#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
+#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
+#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
+#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
+#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
+#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
+#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
-
+
#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
+#include "stm32f4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
+#include "stm32f4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
+#include "stm32f4xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
+#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
+#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
+#include "stm32f4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
+#include "stm32f4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
+#include "stm32f4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) \
+ ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
-
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/