refined stm32 example to pass clang format checker
This commit is contained in:
Donghoon Park
parent
3c23889d47
commit
c321e53391
@ -1,7 +1,7 @@
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BasedOnStyle: LLVM
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AccessModifierOffset: -4
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AlignAfterOpenBracket: Align
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AlignConsecutiveAssignments: None
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AlignConsecutiveAssignments: false
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AlignOperands: Align
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AllowAllArgumentsOnNextLine: false
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AllowAllConstructorInitializersOnNextLine: false
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@ -137,12 +137,10 @@ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY \
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(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
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(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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/* Normal assert() semantics without relying on the provision of an assert.h
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header file. */
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@ -139,8 +139,7 @@ void SystemClock_Config(void) {
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Initialize the CPU, AHB, and APB buses clocks
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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@ -236,15 +235,12 @@ static void MX_SPI1_Init(void) {
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hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
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hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
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hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
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hspi1.Init.CLKPhase =
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SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
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hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
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hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
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hspi1.Init.BaudRatePrescaler =
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SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
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hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
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hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
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hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
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hspi1.Init.CRCCalculation =
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SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
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hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
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hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
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if (HAL_SPI_Init(&hspi1) != HAL_OK) {
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@ -363,16 +359,25 @@ static void MX_DMA_Init(void) {
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void Error_Handler(void) {
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// If an error occurs, stay in infinite loop
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while (1) {
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}
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while (1) {}
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}
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void DMA2_Stream3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); }
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void DMA2_Stream3_IRQHandler(void) {
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HAL_DMA_IRQHandler(&hdma_spi1_tx);
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}
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void DMA2_Stream0_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); }
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void DMA2_Stream0_IRQHandler(void) {
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HAL_DMA_IRQHandler(&hdma_spi1_rx);
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}
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void DMA2_Stream7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_tx); }
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void DMA2_Stream7_IRQHandler(void) {
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HAL_DMA_IRQHandler(&hdma_usart1_tx);
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}
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void DMA2_Stream2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_rx); }
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void DMA2_Stream2_IRQHandler(void) {
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HAL_DMA_IRQHandler(&hdma_usart1_rx);
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}
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void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&huart1); }
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void USART1_IRQHandler(void) {
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HAL_UART_IRQHandler(&huart1);
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}
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@ -121,8 +121,7 @@ extern "C" {
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* @brief External Low Speed oscillator (LSE) value.
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*/
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#if !defined(LSE_VALUE)
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#define LSE_VALUE \
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32768U /*!< Value of the External Low Speed oscillator in Hz */
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#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
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#endif /* LSE_VALUE */
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#if !defined(LSE_STARTUP_TIMEOUT)
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@ -135,8 +134,7 @@ extern "C" {
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* source frequency, this source is inserted directly through I2S_CKIN pad.
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*/
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#if !defined(EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE \
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12288000U /*!< Value of the External oscillator in Hz*/
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#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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@ -153,82 +151,44 @@ extern "C" {
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#define INSTRUCTION_CACHE_ENABLE 1U
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#define DATA_CACHE_ENABLE 1U
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#define USE_HAL_ADC_REGISTER_CALLBACKS \
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0U /* ADC register callback disabled */
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#define USE_HAL_CAN_REGISTER_CALLBACKS \
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0U /* CAN register callback disabled */
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#define USE_HAL_CEC_REGISTER_CALLBACKS \
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0U /* CEC register callback disabled */
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#define USE_HAL_CRYP_REGISTER_CALLBACKS \
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0U /* CRYP register callback disabled */
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#define USE_HAL_DAC_REGISTER_CALLBACKS \
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0U /* DAC register callback disabled */
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#define USE_HAL_DCMI_REGISTER_CALLBACKS \
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0U /* DCMI register callback disabled */
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#define USE_HAL_DFSDM_REGISTER_CALLBACKS \
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0U /* DFSDM register callback disabled */
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#define USE_HAL_DMA2D_REGISTER_CALLBACKS \
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0U /* DMA2D register callback disabled */
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#define USE_HAL_DSI_REGISTER_CALLBACKS \
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0U /* DSI register callback disabled */
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#define USE_HAL_ETH_REGISTER_CALLBACKS \
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0U /* ETH register callback disabled */
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#define USE_HAL_HASH_REGISTER_CALLBACKS \
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0U /* HASH register callback disabled */
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#define USE_HAL_HCD_REGISTER_CALLBACKS \
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0U /* HCD register callback disabled */
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#define USE_HAL_I2C_REGISTER_CALLBACKS \
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0U /* I2C register callback disabled */
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#define USE_HAL_FMPI2C_REGISTER_CALLBACKS \
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0U /* FMPI2C register callback disabled */
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#define USE_HAL_I2S_REGISTER_CALLBACKS \
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0U /* I2S register callback disabled */
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#define USE_HAL_IRDA_REGISTER_CALLBACKS \
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0U /* IRDA register callback disabled */
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#define USE_HAL_LPTIM_REGISTER_CALLBACKS \
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0U /* LPTIM register callback disabled */
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#define USE_HAL_LTDC_REGISTER_CALLBACKS \
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0U /* LTDC register callback disabled */
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#define USE_HAL_MMC_REGISTER_CALLBACKS \
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0U /* MMC register callback disabled */
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#define USE_HAL_NAND_REGISTER_CALLBACKS \
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0U /* NAND register callback disabled */
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#define USE_HAL_NOR_REGISTER_CALLBACKS \
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0U /* NOR register callback disabled */
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#define USE_HAL_PCCARD_REGISTER_CALLBACKS \
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0U /* PCCARD register callback disabled */
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#define USE_HAL_PCD_REGISTER_CALLBACKS \
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0U /* PCD register callback disabled */
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#define USE_HAL_QSPI_REGISTER_CALLBACKS \
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0U /* QSPI register callback disabled */
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#define USE_HAL_RNG_REGISTER_CALLBACKS \
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0U /* RNG register callback disabled */
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#define USE_HAL_RTC_REGISTER_CALLBACKS \
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0U /* RTC register callback disabled */
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#define USE_HAL_SAI_REGISTER_CALLBACKS \
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0U /* SAI register callback disabled */
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#define USE_HAL_SD_REGISTER_CALLBACKS \
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0U /* SD register callback disabled */
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#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS \
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0U /* SMARTCARD register callback disabled */
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#define USE_HAL_SDRAM_REGISTER_CALLBACKS \
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0U /* SDRAM register callback disabled */
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#define USE_HAL_SRAM_REGISTER_CALLBACKS \
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0U /* SRAM register callback disabled */
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#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS \
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0U /* SPDIFRX register callback disabled */
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#define USE_HAL_SMBUS_REGISTER_CALLBACKS \
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0U /* SMBUS register callback disabled */
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#define USE_HAL_SPI_REGISTER_CALLBACKS \
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0U /* SPI register callback disabled */
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#define USE_HAL_TIM_REGISTER_CALLBACKS \
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0U /* TIM register callback disabled */
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#define USE_HAL_UART_REGISTER_CALLBACKS \
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0U /* UART register callback disabled */
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#define USE_HAL_USART_REGISTER_CALLBACKS \
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0U /* USART register callback disabled */
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#define USE_HAL_WWDG_REGISTER_CALLBACKS \
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0U /* WWDG register callback disabled */
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#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
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#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
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#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
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#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
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#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
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#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
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#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
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#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
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#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
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#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
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#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
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#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
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#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
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#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
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#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
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#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
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#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
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#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
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#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
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#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
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#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
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#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
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#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
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#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
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#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
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#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
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#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
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#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
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#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
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#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
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#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
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#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
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#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
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#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
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#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
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#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
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#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
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#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
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/* ########################## Assert Selection ############################## */
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/**
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@ -250,10 +210,8 @@ extern "C" {
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#define MAC_ADDR5 0U
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE \
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ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE \
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ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
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@ -276,55 +234,34 @@ extern "C" {
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#define PHY_RESET ((uint16_t) 0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t) 0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M \
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((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M \
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((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M \
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((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M \
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((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION \
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((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION \
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((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN \
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((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE \
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((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_FULLDUPLEX_100M ((uint16_t) 0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t) 0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t) 0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t) 0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t) 0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t) 0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t) 0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t) 0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE \
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((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS \
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((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION \
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((uint16_t)0x0002) /*!< Jabber condition detected */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t) 0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t) 0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t) 0x0002) /*!< Jabber condition detected */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR \
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((uint16_t)0x0010) /*!< PHY status register Offset */
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#define PHY_MICR \
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((uint16_t)0x0011) /*!< MII Interrupt Control Register */
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#define PHY_MISR \
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((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_SR ((uint16_t) 0x0010) /*!< PHY status register Offset */
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#define PHY_MICR ((uint16_t) 0x0011) /*!< MII Interrupt Control Register */
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#define PHY_MISR ((uint16_t) 0x0012) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_LINK_STATUS \
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((uint16_t)0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS \
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((uint16_t)0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS \
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((uint16_t)0x0004) /*!< PHY Duplex mask */
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#define PHY_LINK_STATUS ((uint16_t) 0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS ((uint16_t) 0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t) 0x0004) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN \
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((uint16_t)0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE \
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((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MICR_INT_EN ((uint16_t) 0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t) 0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN \
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((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT \
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((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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#define PHY_MISR_LINK_INT_EN ((uint16_t) 0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT ((uint16_t) 0x2000) /*!< PHY link status interrupt mask */
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/* ################## SPI peripheral configuration ########################## */
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@ -542,8 +479,7 @@ extern "C" {
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* If expr is true, it returns no value.
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* @retval None
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*/
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#define assert_param(expr) \
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((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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#define assert_param(expr) ((expr) ? (void) 0U : assert_failed((uint8_t*) __FILE__, __LINE__))
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/* Exported functions ------------------------------------------------------- */
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void assert_failed(uint8_t* file, uint32_t line);
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#else
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