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refined stm32 example to pass clang format checker

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This commit is contained in:
Donghoon Park 2024-12-15 03:30:40 +00:00
parent 3c23889d47
commit c321e53391
4 changed files with 300 additions and 361 deletions
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2
.clang-format
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@ -1,7 +1,7 @@
BasedOnStyle: LLVM BasedOnStyle: LLVM
AccessModifierOffset: -4 AccessModifierOffset: -4
AlignAfterOpenBracket: Align AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: None AlignConsecutiveAssignments: false
AlignOperands: Align AlignOperands: Align
AllowAllArgumentsOnNextLine: false AllowAllArgumentsOnNextLine: false
AllowAllConstructorInitializersOnNextLine: false AllowAllConstructorInitializersOnNextLine: false

12
examples/stm32/FreeRTOSConfig.h
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@ -47,7 +47,7 @@ extern uint32_t SystemCoreClock;
#if defined STM32L5 #if defined STM32L5
#define configENABLE_TRUSTZONE 0 #define configENABLE_TRUSTZONE 0
#if configENABLE_TRUSTZONE #if configENABLE_TRUSTZONE
#define configMINIMAL_SECURE_STACK_SIZE ((uint16_t)1024) #define configMINIMAL_SECURE_STACK_SIZE ((uint16_t) 1024)
#endif #endif
#define configRUN_FREERTOS_SECURE_ONLY 0 #define configRUN_FREERTOS_SECURE_ONLY 0
#define configENABLE_FPU 1 #define configENABLE_FPU 1
@ -58,11 +58,11 @@ extern uint32_t SystemCoreClock;
#define configUSE_IDLE_HOOK 0 #define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0 #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ (SystemCoreClock) #define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ ((TickType_t)1000) #define configTICK_RATE_HZ ((TickType_t) 1000)
#if !defined USE_CMSIS_RTOS_V2 #if !defined USE_CMSIS_RTOS_V2
#define configMAX_PRIORITIES (5) #define configMAX_PRIORITIES (5)
#endif #endif
#define configMINIMAL_STACK_SIZE ((unsigned short)50) #define configMINIMAL_STACK_SIZE ((unsigned short) 50)
#define configTOTAL_HEAP_SIZE ((size_t)(32 * 1024)) #define configTOTAL_HEAP_SIZE ((size_t)(32 * 1024))
#define configMAX_TASK_NAME_LEN (10) #define configMAX_TASK_NAME_LEN (10)
#define configUSE_TRACE_FACILITY 1 #define configUSE_TRACE_FACILITY 1
@ -137,12 +137,10 @@ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
/* Interrupt priorities used by the kernel port layer itself. These are generic /* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */ to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY \ #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \ #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
header file. */ header file. */

35
examples/stm32/bsp/blackpill/blackpill.c
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@ -139,8 +139,7 @@ void SystemClock_Config(void) {
HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_RCC_OscConfig(&RCC_OscInitStruct);
// Initialize the CPU, AHB, and APB buses clocks // Initialize the CPU, AHB, and APB buses clocks
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
@ -236,15 +235,12 @@ static void MX_SPI1_Init(void) {
hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
hspi1.Init.CLKPhase = hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
hspi1.Init.BaudRatePrescaler = hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
hspi1.Init.CRCCalculation = hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
hspi1.Init.CRCPolynomial = 10; // CRC polynomial value hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
if (HAL_SPI_Init(&hspi1) != HAL_OK) { if (HAL_SPI_Init(&hspi1) != HAL_OK) {
@ -363,16 +359,25 @@ static void MX_DMA_Init(void) {
void Error_Handler(void) { void Error_Handler(void) {
// If an error occurs, stay in infinite loop // If an error occurs, stay in infinite loop
while (1) { while (1) {}
}
} }
void DMA2_Stream3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); } void DMA2_Stream3_IRQHandler(void) {
HAL_DMA_IRQHandler(&hdma_spi1_tx);
}
void DMA2_Stream0_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); } void DMA2_Stream0_IRQHandler(void) {
HAL_DMA_IRQHandler(&hdma_spi1_rx);
}
void DMA2_Stream7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_tx); } void DMA2_Stream7_IRQHandler(void) {
HAL_DMA_IRQHandler(&hdma_usart1_tx);
}
void DMA2_Stream2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_rx); } void DMA2_Stream2_IRQHandler(void) {
HAL_DMA_IRQHandler(&hdma_usart1_rx);
}
void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&huart1); } void USART1_IRQHandler(void) {
HAL_UART_IRQHandler(&huart1);
}

204
examples/stm32/stm32f4xx_hal_conf.h
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@ -121,8 +121,7 @@ extern "C" {
* @brief External Low Speed oscillator (LSE) value. * @brief External Low Speed oscillator (LSE) value.
*/ */
#if !defined(LSE_VALUE) #if !defined(LSE_VALUE)
#define LSE_VALUE \ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined(LSE_STARTUP_TIMEOUT) #if !defined(LSE_STARTUP_TIMEOUT)
@ -135,8 +134,7 @@ extern "C" {
* source frequency, this source is inserted directly through I2S_CKIN pad. * source frequency, this source is inserted directly through I2S_CKIN pad.
*/ */
#if !defined(EXTERNAL_CLOCK_VALUE) #if !defined(EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE \ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
12288000U /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */ #endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,
@ -153,82 +151,44 @@ extern "C" {
#define INSTRUCTION_CACHE_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS \ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
0U /* ADC register callback disabled */ #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS \ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
0U /* CAN register callback disabled */ #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS \ #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
0U /* CEC register callback disabled */ #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS \ #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
0U /* CRYP register callback disabled */ #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS \ #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
0U /* DAC register callback disabled */ #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS \ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
0U /* DCMI register callback disabled */ #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS \ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
0U /* DFSDM register callback disabled */ #define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS \ #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
0U /* DMA2D register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS \ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
0U /* DSI register callback disabled */ #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS \ #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
0U /* ETH register callback disabled */ #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS \ #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
0U /* HASH register callback disabled */ #define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS \ #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
0U /* HCD register callback disabled */ #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS \ #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
0U /* I2C register callback disabled */ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS \ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
0U /* FMPI2C register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS \ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
0U /* I2S register callback disabled */ #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS \ #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
0U /* IRDA register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS \ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
0U /* LPTIM register callback disabled */ #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS \ #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
0U /* LTDC register callback disabled */ #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS \ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
0U /* MMC register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS \
0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS \
0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS \
0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS \
0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS \
0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS \
0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS \
0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS \
0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS \
0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS \
0U /* SMARTCARD register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS \
0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS \
0U /* SRAM register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS \
0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS \
0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS \
0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS \
0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS \
0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS \
0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS \
0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**
@ -250,10 +210,8 @@ extern "C" {
#define MAC_ADDR5 0U #define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */ /* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE \ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_TX_BUF_SIZE \
ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
@ -271,60 +229,39 @@ extern "C" {
/* Section 3: Common PHY Registers */ /* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BCR ((uint16_t) 0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ #define PHY_BSR ((uint16_t) 0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_RESET ((uint16_t) 0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_LOOPBACK ((uint16_t) 0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M \ #define PHY_FULLDUPLEX_100M ((uint16_t) 0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ #define PHY_HALFDUPLEX_100M ((uint16_t) 0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M \ #define PHY_FULLDUPLEX_10M ((uint16_t) 0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ #define PHY_HALFDUPLEX_10M ((uint16_t) 0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_FULLDUPLEX_10M \ #define PHY_AUTONEGOTIATION ((uint16_t) 0x1000) /*!< Enable auto-negotiation function */
((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ #define PHY_RESTART_AUTONEGOTIATION ((uint16_t) 0x0200) /*!< Restart auto-negotiation function */
#define PHY_HALFDUPLEX_10M \ #define PHY_POWERDOWN ((uint16_t) 0x0800) /*!< Select the power down mode */
((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ #define PHY_ISOLATE ((uint16_t) 0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGOTIATION \
((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION \
((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN \
((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE \
((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE \ #define PHY_AUTONEGO_COMPLETE ((uint16_t) 0x0020) /*!< Auto-Negotiation process completed */
((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t) 0x0004) /*!< Valid link established */
#define PHY_LINKED_STATUS \ #define PHY_JABBER_DETECTION ((uint16_t) 0x0002) /*!< Jabber condition detected */
((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION \
((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */ /* Section 4: Extended PHY Registers */
#define PHY_SR \ #define PHY_SR ((uint16_t) 0x0010) /*!< PHY status register Offset */
((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t) 0x0011) /*!< MII Interrupt Control Register */
#define PHY_MICR \ #define PHY_MISR ((uint16_t) 0x0012) /*!< MII Interrupt Status and Misc. Control Register */
((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR \
((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS \ #define PHY_LINK_STATUS ((uint16_t) 0x0001) /*!< PHY Link mask */
((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t) 0x0002) /*!< PHY Speed mask */
#define PHY_SPEED_STATUS \ #define PHY_DUPLEX_STATUS ((uint16_t) 0x0004) /*!< PHY Duplex mask */
((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS \
((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN \ #define PHY_MICR_INT_EN ((uint16_t) 0x0002) /*!< PHY Enable interrupts */
((uint16_t)0x0002) /*!< PHY Enable interrupts */ #define PHY_MICR_INT_OE ((uint16_t) 0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MICR_INT_OE \
((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN \ #define PHY_MISR_LINK_INT_EN ((uint16_t) 0x0020) /*!< Enable Interrupt on change of link status */
((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ #define PHY_LINK_INTERRUPT ((uint16_t) 0x2000) /*!< PHY link status interrupt mask */
#define PHY_LINK_INTERRUPT \
((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */
@ -542,12 +479,11 @@ extern "C" {
* If expr is true, it returns no value. * If expr is true, it returns no value.
* @retval None * @retval None
*/ */
#define assert_param(expr) \ #define assert_param(expr) ((expr) ? (void) 0U : assert_failed((uint8_t*) __FILE__, __LINE__))
((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */ /* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line); void assert_failed(uint8_t* file, uint32_t line);
#else #else
#define assert_param(expr) ((void)0U) #define assert_param(expr) ((void) 0U)
#endif /* USE_FULL_ASSERT */ #endif /* USE_FULL_ASSERT */
#ifdef __cplusplus #ifdef __cplusplus