refined stm32 example to pass clang format checker
This commit is contained in:
Donghoon Park
parent
3c23889d47
commit
c321e53391
@ -1,7 +1,7 @@
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BasedOnStyle: LLVM
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AccessModifierOffset: -4
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AlignAfterOpenBracket: Align
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AlignConsecutiveAssignments: None
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AlignConsecutiveAssignments: false
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AlignOperands: Align
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AllowAllArgumentsOnNextLine: false
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AllowAllConstructorInitializersOnNextLine: false
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@ -47,7 +47,7 @@ extern uint32_t SystemCoreClock;
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#if defined STM32L5
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#define configENABLE_TRUSTZONE 0
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#if configENABLE_TRUSTZONE
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#define configMINIMAL_SECURE_STACK_SIZE ((uint16_t)1024)
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#define configMINIMAL_SECURE_STACK_SIZE ((uint16_t) 1024)
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#endif
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#define configRUN_FREERTOS_SECURE_ONLY 0
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#define configENABLE_FPU 1
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@ -58,11 +58,11 @@ extern uint32_t SystemCoreClock;
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ (SystemCoreClock)
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#define configTICK_RATE_HZ ((TickType_t)1000)
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#define configTICK_RATE_HZ ((TickType_t) 1000)
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#if !defined USE_CMSIS_RTOS_V2
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#define configMAX_PRIORITIES (5)
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#endif
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#define configMINIMAL_STACK_SIZE ((unsigned short)50)
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#define configMINIMAL_STACK_SIZE ((unsigned short) 50)
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#define configTOTAL_HEAP_SIZE ((size_t)(32 * 1024))
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#define configMAX_TASK_NAME_LEN (10)
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#define configUSE_TRACE_FACILITY 1
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@ -137,21 +137,19 @@ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY \
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(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
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(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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/* Normal assert() semantics without relying on the provision of an assert.h
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header file. */
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#define configASSERT(x) \
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if ((x) == 0) { \
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taskDISABLE_INTERRUPTS(); \
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for (;;) \
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; \
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}
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#define configASSERT(x) \
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if ((x) == 0) { \
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taskDISABLE_INTERRUPTS(); \
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for (;;) \
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; \
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}
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/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
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standard names. */
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@ -109,270 +109,275 @@ DMA_HandleTypeDef hdma_usart1_tx;
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DMA_HandleTypeDef hdma_usart1_rx;
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void BSP_Init(void) {
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// Initialize the HAL Library
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HAL_Init();
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// Initialize the HAL Library
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HAL_Init();
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// Configure the system clock
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SystemClock_Config();
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// Configure the system clock
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SystemClock_Config();
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// Initialize all configured peripherals (GPIO and SPI1)
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MX_GPIO_Init();
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MX_SPI1_Init();
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MX_DMA_Init();
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MX_USART1_UART_Init();
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// Initialize all configured peripherals (GPIO and SPI1)
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MX_GPIO_Init();
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MX_SPI1_Init();
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MX_DMA_Init();
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MX_USART1_UART_Init();
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}
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void SystemClock_Config(void) {
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// System Clock Configuration Code
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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// System Clock Configuration Code
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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// Configure the main internal regulator output voltage
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Configure the main internal regulator output voltage
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Initialize the CPU, AHB, and APB buses clocks
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
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// Initialize the CPU, AHB, and APB buses clocks
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
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}
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static void MX_GPIO_Init(void) {
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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// Enable GPIOC clock
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__HAL_RCC_GPIOC_CLK_ENABLE();
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// Enable GPIOC clock
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__HAL_RCC_GPIOC_CLK_ENABLE();
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// Configure GPIOC Pin 13 for LED output (Output Push Pull mode)
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GPIO_InitStruct.Pin = GPIO_PIN_13;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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// Configure GPIOC Pin 13 for LED output (Output Push Pull mode)
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GPIO_InitStruct.Pin = GPIO_PIN_13;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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// Enable GPIOB clock
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__HAL_RCC_GPIOB_CLK_ENABLE();
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// Enable GPIOB clock
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__HAL_RCC_GPIOB_CLK_ENABLE();
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// Configure GPIOB Pin 7 as input for interrupt (Input mode)
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GPIO_InitStruct.Pin = GPIO_PIN_7;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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// Configure GPIOB Pin 7 as input for interrupt (Input mode)
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GPIO_InitStruct.Pin = GPIO_PIN_7;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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// Configure GPIOB Pin 6 as output with Open Drain mode
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GPIO_InitStruct.Pin = GPIO_PIN_6;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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// Configure GPIOB Pin 6 as output with Open Drain mode
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GPIO_InitStruct.Pin = GPIO_PIN_6;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);
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HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);
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// Enable GPIOA clock
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// Configure NSS pin (PA15) as Output Push Pull
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GPIO_InitStruct.Pin = GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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// Enable GPIOA clock
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// Configure NSS pin (PA15) as Output Push Pull
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GPIO_InitStruct.Pin = GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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static void MX_USART1_UART_Init(void) {
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// USART1 initialization settings
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__HAL_RCC_USART1_CLK_ENABLE();
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// USART1 initialization settings
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__HAL_RCC_USART1_CLK_ENABLE();
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huart1.Instance = USART1;
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huart1.Init.BaudRate = 115200;
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huart1.Init.WordLength = UART_WORDLENGTH_8B;
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huart1.Init.StopBits = UART_STOPBITS_1;
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huart1.Init.Parity = UART_PARITY_NONE;
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huart1.Init.Mode = UART_MODE_TX_RX;
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huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
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huart1.Init.OverSampling = UART_OVERSAMPLING_16;
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huart1.Instance = USART1;
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huart1.Init.BaudRate = 115200;
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huart1.Init.WordLength = UART_WORDLENGTH_8B;
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huart1.Init.StopBits = UART_STOPBITS_1;
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huart1.Init.Parity = UART_PARITY_NONE;
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huart1.Init.Mode = UART_MODE_TX_RX;
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huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
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huart1.Init.OverSampling = UART_OVERSAMPLING_16;
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if (HAL_UART_Init(&huart1) != HAL_OK) {
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// Initialization error handling
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Error_Handler();
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}
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if (HAL_UART_Init(&huart1) != HAL_OK) {
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// Initialization error handling
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Error_Handler();
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}
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// Enable USART1 interrupt
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// It must higher or equal than 5
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HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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// Enable USART1 interrupt
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// It must higher or equal than 5
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HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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// USART1 Pin configuration: TX (PA9), RX (PA10)
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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// USART1 Pin configuration: TX (PA9), RX (PA10)
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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// Enable GPIOA clock
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// Enable GPIOA clock
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push
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// Pull
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GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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// Configure USART1 TX (PA9) and RX (PA10) pins as Alternate Function Push
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// Pull
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GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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static void MX_SPI1_Init(void) {
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__HAL_RCC_SPI1_CLK_ENABLE();
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// SPI1 initialization settings
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hspi1.Instance = SPI1;
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hspi1.Init.Mode = SPI_MODE_MASTER; // Set SPI1 as master
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hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
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hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
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hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
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hspi1.Init.CLKPhase =
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SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
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hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
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hspi1.Init.BaudRatePrescaler =
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SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
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hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
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hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
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hspi1.Init.CRCCalculation =
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SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
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hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
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__HAL_RCC_SPI1_CLK_ENABLE();
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// SPI1 initialization settings
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hspi1.Instance = SPI1;
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hspi1.Init.Mode = SPI_MODE_MASTER; // Set SPI1 as master
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hspi1.Init.Direction = SPI_DIRECTION_2LINES; // Set bidirectional data mode
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hspi1.Init.DataSize = SPI_DATASIZE_8BIT; // Set data frame size to 8 bits
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hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // Clock polarity low when idle
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hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; // First clock transition is the first data capture edge
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hspi1.Init.NSS = SPI_NSS_SOFT; // Hardware chip select management
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hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // Set baud rate prescaler to 2
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hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; // Data is transmitted MSB first
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hspi1.Init.TIMode = SPI_TIMODE_DISABLE; // Disable TI mode
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hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; // Disable CRC calculation
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hspi1.Init.CRCPolynomial = 10; // CRC polynomial value
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if (HAL_SPI_Init(&hspi1) != HAL_OK) {
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// Initialization error handling
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Error_Handler();
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}
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if (HAL_SPI_Init(&hspi1) != HAL_OK) {
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// Initialization error handling
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Error_Handler();
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}
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// SPI1 Pin configuration: SCLK (PB3), MISO (PB4), MOSI (PB5)
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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// SPI1 Pin configuration: SCLK (PB3), MISO (PB4), MOSI (PB5)
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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// Enable GPIOB clock
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__HAL_RCC_GPIOB_CLK_ENABLE();
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// Enable GPIOB clock
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__HAL_RCC_GPIOB_CLK_ENABLE();
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// Configure SPI1 SCLK, MISO, MOSI pins as Alternate Function Push Pull
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GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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// Configure SPI1 SCLK, MISO, MOSI pins as Alternate Function Push Pull
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GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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}
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static void MX_DMA_Init(void) {
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// DMA controller clock enable
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__HAL_RCC_DMA2_CLK_ENABLE();
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// DMA controller clock enable
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__HAL_RCC_DMA2_CLK_ENABLE();
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// Configure DMA request hdma_spi1_tx on DMA2_Stream3
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hdma_spi1_tx.Instance = DMA2_Stream3;
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hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3;
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hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
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hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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hdma_spi1_tx.Init.Mode = DMA_NORMAL;
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hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
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hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) {
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// Initialization error handling
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Error_Handler();
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}
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// Configure DMA request hdma_spi1_tx on DMA2_Stream3
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hdma_spi1_tx.Instance = DMA2_Stream3;
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hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3;
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hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
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hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
|
||||
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&hspi1, hdmatx, hdma_spi1_tx);
|
||||
__HAL_LINKDMA(&hspi1, hdmatx, hdma_spi1_tx);
|
||||
|
||||
// Configure DMA request hdma_spi1_rx on DMA2_Stream0
|
||||
hdma_spi1_rx.Instance = DMA2_Stream0;
|
||||
hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3;
|
||||
hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
// Configure DMA request hdma_spi1_rx on DMA2_Stream0
|
||||
hdma_spi1_rx.Instance = DMA2_Stream0;
|
||||
hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3;
|
||||
hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&hspi1, hdmarx, hdma_spi1_rx);
|
||||
__HAL_LINKDMA(&hspi1, hdmarx, hdma_spi1_rx);
|
||||
|
||||
// Configure DMA request hdma_usart1_tx on DMA2_Stream7
|
||||
hdma_usart1_tx.Instance = DMA2_Stream7;
|
||||
hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
|
||||
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
// Configure DMA request hdma_usart1_tx on DMA2_Stream7
|
||||
hdma_usart1_tx.Instance = DMA2_Stream7;
|
||||
hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
|
||||
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&huart1, hdmatx, hdma_usart1_tx);
|
||||
__HAL_LINKDMA(&huart1, hdmatx, hdma_usart1_tx);
|
||||
|
||||
// Configure DMA request hdma_usart1_rx on DMA2_Stream2
|
||||
hdma_usart1_rx.Instance = DMA2_Stream2;
|
||||
hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4;
|
||||
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
// Configure DMA request hdma_usart1_rx on DMA2_Stream2
|
||||
hdma_usart1_rx.Instance = DMA2_Stream2;
|
||||
hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4;
|
||||
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
|
||||
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) {
|
||||
// Initialization error handling
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&huart1, hdmarx, hdma_usart1_rx);
|
||||
__HAL_LINKDMA(&huart1, hdmarx, hdma_usart1_rx);
|
||||
|
||||
// DMA2_Stream3 (SPI1_TX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
|
||||
// DMA2_Stream3 (SPI1_TX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
|
||||
|
||||
// DMA2_Stream0 (SPI1_RX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
|
||||
// DMA2_Stream0 (SPI1_RX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
|
||||
|
||||
// DMA2_Stream7 (USART1_TX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
||||
// DMA2_Stream7 (USART1_TX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
||||
|
||||
// DMA2_Stream2 (USART1_RX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
||||
// DMA2_Stream2 (USART1_RX) Interrupt Configuration
|
||||
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
||||
}
|
||||
|
||||
void Error_Handler(void) {
|
||||
// If an error occurs, stay in infinite loop
|
||||
while (1) {
|
||||
}
|
||||
// If an error occurs, stay in infinite loop
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
void DMA2_Stream3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); }
|
||||
void DMA2_Stream3_IRQHandler(void) {
|
||||
HAL_DMA_IRQHandler(&hdma_spi1_tx);
|
||||
}
|
||||
|
||||
void DMA2_Stream0_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); }
|
||||
void DMA2_Stream0_IRQHandler(void) {
|
||||
HAL_DMA_IRQHandler(&hdma_spi1_rx);
|
||||
}
|
||||
|
||||
void DMA2_Stream7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_tx); }
|
||||
void DMA2_Stream7_IRQHandler(void) {
|
||||
HAL_DMA_IRQHandler(&hdma_usart1_tx);
|
||||
}
|
||||
|
||||
void DMA2_Stream2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_usart1_rx); }
|
||||
void DMA2_Stream2_IRQHandler(void) {
|
||||
HAL_DMA_IRQHandler(&hdma_usart1_rx);
|
||||
}
|
||||
|
||||
void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&huart1); }
|
||||
void USART1_IRQHandler(void) {
|
||||
HAL_UART_IRQHandler(&huart1);
|
||||
}
|
||||
|
||||
@ -121,9 +121,8 @@ extern "C" {
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined(LSE_VALUE)
|
||||
#define LSE_VALUE \
|
||||
32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined(LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
@ -135,9 +134,8 @@ extern "C" {
|
||||
* source frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined(EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE \
|
||||
12288000U /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
@ -153,82 +151,44 @@ extern "C" {
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS \
|
||||
0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS \
|
||||
0U /* CAN register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS \
|
||||
0U /* CEC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS \
|
||||
0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS \
|
||||
0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS \
|
||||
0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS \
|
||||
0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS \
|
||||
0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS \
|
||||
0U /* DSI register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS \
|
||||
0U /* ETH register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS \
|
||||
0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS \
|
||||
0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS \
|
||||
0U /* I2C register callback disabled */
|
||||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS \
|
||||
0U /* FMPI2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS \
|
||||
0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS \
|
||||
0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS \
|
||||
0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS \
|
||||
0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS \
|
||||
0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS \
|
||||
0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS \
|
||||
0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS \
|
||||
0U /* PCCARD register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS \
|
||||
0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS \
|
||||
0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS \
|
||||
0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS \
|
||||
0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS \
|
||||
0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS \
|
||||
0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS \
|
||||
0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS \
|
||||
0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS \
|
||||
0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS \
|
||||
0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS \
|
||||
0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS \
|
||||
0U /* SPI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS \
|
||||
0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS \
|
||||
0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS \
|
||||
0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS \
|
||||
0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
@ -250,12 +210,10 @@ extern "C" {
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE \
|
||||
ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE \
|
||||
ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
@ -271,60 +229,39 @@ extern "C" {
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
|
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#define PHY_BCR ((uint16_t) 0x0000) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t) 0x0001) /*!< Transceiver Basic Status Register */
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||||
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M \
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((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M \
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((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M \
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((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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||||
#define PHY_HALFDUPLEX_10M \
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((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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||||
#define PHY_AUTONEGOTIATION \
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((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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||||
#define PHY_RESTART_AUTONEGOTIATION \
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((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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||||
#define PHY_POWERDOWN \
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||||
((uint16_t)0x0800) /*!< Select the power down mode */
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||||
#define PHY_ISOLATE \
|
||||
((uint16_t)0x0400) /*!< Isolate PHY from MII */
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||||
#define PHY_RESET ((uint16_t) 0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t) 0x4000) /*!< Select loop-back mode */
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||||
#define PHY_FULLDUPLEX_100M ((uint16_t) 0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t) 0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t) 0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t) 0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t) 0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t) 0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t) 0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t) 0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE \
|
||||
((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS \
|
||||
((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION \
|
||||
((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t) 0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t) 0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t) 0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR \
|
||||
((uint16_t)0x0010) /*!< PHY status register Offset */
|
||||
#define PHY_MICR \
|
||||
((uint16_t)0x0011) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR \
|
||||
((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
#define PHY_SR ((uint16_t) 0x0010) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t) 0x0011) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t) 0x0012) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS \
|
||||
((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS \
|
||||
((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS \
|
||||
((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
#define PHY_LINK_STATUS ((uint16_t) 0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t) 0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t) 0x0004) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN \
|
||||
((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE \
|
||||
((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
#define PHY_MICR_INT_EN ((uint16_t) 0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t) 0x0001) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN \
|
||||
((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT \
|
||||
((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t) 0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t) 0x2000) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
@ -542,12 +479,11 @@ extern "C" {
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) \
|
||||
((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
#define assert_param(expr) ((expr) ? (void) 0U : assert_failed((uint8_t*) __FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#define assert_param(expr) ((void) 0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Loading…
Reference in New Issue
Block a user