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RLC-Circuit-Analysis-and-Optimization
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f60e76d7d2
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judsonupchurch
f60e76d7d2
Reorganize
2025-12-12 18:16:36 -06:00
gnd_plane_reflection
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2025-12-12 18:16:36 -06:00
impedance_mismatch_no_gnd_plane_split
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2025-12-12 18:16:36 -06:00
LtSpice
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main.py
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README.md
Initial commit, test mirror
2025-12-10 13:42:18 -06:00
README.md
