Readme updated with example results
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# Purpose
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The purpose of this simulation class is to provide a simple, resistor-inductor-capacitor (RLC) circuit solver. Currently, it can perform a transient simulation given a time-varying input. It has personally provided a better intuition on certain effects such as routing a PCB trace over a ground plane split or an impedance mismatch between the source and the load.
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Next steps are to provide an adjoint parameter optimizer for optimizing the network for impedance matching or any other cost-quantifiable objective.
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# Examples
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## Ground Plane Split Example 1
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In this example, the source and load are matched but there is a split in a ground plane.
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The representative circuit is shown below. The split in the ground plane is modeled by creating a separate, "local ground" on the right side of the circuit that as an inductor and capacitor branch and a parallel resistor connecting it to the true ground.
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The LTspice results are shown below.
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The LTspice results are compared to the Python simulation. results
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## Ground Plane Split Example 2
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In this example, the source and load are matched but there is a split in a ground plane. It varies with the prior example by changing key component values in the model, providing a completely different response.
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Circuit
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The results of the simulation are below.
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## Ground Plane Split with Mismatched Load
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This example includes both the ground plate split and a mismatched source and load impedance.
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The circuit in LTspice is shown below
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The LTspice simulation results are below
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A comparison between the LTspice simulation and Python simulation are below
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