Fixes after STM32 example merge
This commit is contained in:
Valerio De Benedetto
parent
3bf5ed37c8
commit
c660369a43
@ -2,10 +2,10 @@ cmake_minimum_required(VERSION 3.16)
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set(PROJ_NAME stm32-blackpill)
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include(FetchContent)
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FetchContent_Declare( stm32_cmake
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GIT_REPOSITORY https://github.com/ObKo/stm32-cmake
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GIT_TAG v2.1.0
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GIT_SHALLOW TRUE
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FetchContent_Declare(stm32_cmake
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GIT_REPOSITORY https://github.com/ObKo/stm32-cmake
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GIT_TAG v2.1.0
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GIT_SHALLOW TRUE
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)
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FetchContent_Populate(stm32_cmake)
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set(CMAKE_TOOLCHAIN_FILE ${stm32_cmake_SOURCE_DIR}/cmake/stm32_gcc.cmake)
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@ -20,24 +20,24 @@ find_package(CMSIS COMPONENTS STM32F401CC REQUIRED)
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find_package(HAL COMPONENTS STM32F4 REQUIRED)
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add_compile_options(
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-mcpu=cortex-m4
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-mfpu=fpv4-sp-d16
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-mfloat-abi=hard
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)
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-mcpu=cortex-m4
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-mfpu=fpv4-sp-d16
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-mfloat-abi=hard
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)
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set(CMAKE_INCLUDE_CURRENT_DIR ON)
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set( FREERTOS_HEAP "4")
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set( FREERTOS_PORT "GCC_ARM_CM4F")
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set(FREERTOS_HEAP "4")
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set(FREERTOS_PORT "GCC_ARM_CM4F")
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add_library(freertos_config INTERFACE)
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target_include_directories(freertos_config SYSTEM
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INTERFACE
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${CMAKE_CURRENT_SOURCE_DIR}
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)
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FetchContent_Declare( freertos_kernel
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GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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GIT_TAG V11.1.0
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GIT_SHALLOW TRUE
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INTERFACE
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${CMAKE_CURRENT_SOURCE_DIR}
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)
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FetchContent_Declare(freertos_kernel
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GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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GIT_TAG V11.1.0
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GIT_SHALLOW TRUE
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)
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FetchContent_MakeAvailable(freertos_kernel)
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@ -45,82 +45,82 @@ FetchContent_MakeAvailable(freertos_kernel)
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set(WIZ_CHIP W5500)
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FetchContent_Declare(
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wizchip
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GIT_REPOSITORY https://github.com/donghoonpark/wizchip-cmake
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GIT_SHALLOW TRUE
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wizchip
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GIT_REPOSITORY https://github.com/donghoonpark/wizchip-cmake
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GIT_SHALLOW TRUE
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)
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FetchContent_MakeAvailable(wizchip)
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FetchContent_Declare(
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nanomodbus
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GIT_REPOSITORY https://github.com/debevv/nanoMODBUS
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GIT_TAG v1.18.1
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GIT_SHALLOW TRUE
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nanomodbus
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GIT_REPOSITORY https://github.com/debevv/nanoMODBUS
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GIT_TAG v1.18.1
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GIT_SHALLOW TRUE
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)
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FetchContent_GetProperties(nanomodbus)
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if(NOT nanomodbus_POPULATED)
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FetchContent_Populate(nanomodbus)
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endif()
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if (NOT nanomodbus_POPULATED)
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FetchContent_Populate(nanomodbus)
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endif ()
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add_library(nanomodbus ${nanomodbus_SOURCE_DIR}/nanomodbus.c)
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target_include_directories(nanomodbus PUBLIC ${nanomodbus_SOURCE_DIR})
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set(TARGET_NAMES modbus_rtu modbus_tcp)
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foreach(TARGET_NAME ${TARGET_NAMES})
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foreach (TARGET_NAME ${TARGET_NAMES})
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add_executable(${TARGET_NAME}
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${TARGET_NAME}.c
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bsp/blackpill/blackpill.c
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nmbs/port.c
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)
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target_include_directories(
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${TARGET_NAME} PRIVATE
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${CMAKE_CURRENT_SOURCE_DIR}/bsp
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${CMAKE_CURRENT_SOURCE_DIR}/nmbs
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)
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if(${TARGET_NAME} STREQUAL "modbus_rtu")
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target_compile_definitions(
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${TARGET_NAME} PRIVATE
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NMBS_RTU
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add_executable(${TARGET_NAME}
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${TARGET_NAME}.c
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bsp/blackpill/blackpill.c
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nmbs/port.c
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)
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elseif(${TARGET_NAME} STREQUAL "modbus_tcp")
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target_compile_definitions(
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${TARGET_NAME} PRIVATE
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NMBS_TCP
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target_include_directories(
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${TARGET_NAME} PRIVATE
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${CMAKE_CURRENT_SOURCE_DIR}/bsp
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${CMAKE_CURRENT_SOURCE_DIR}/nmbs
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)
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endif()
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target_link_libraries(
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${TARGET_NAME}
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STM32::NoSys
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CMSIS::STM32::F401CC
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HAL::STM32::F4::CORTEX
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HAL::STM32::F4::RCC
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HAL::STM32::F4::PWR
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HAL::STM32::F4::GPIO
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HAL::STM32::F4::TIM
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HAL::STM32::F4::UART
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HAL::STM32::F4::USART
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HAL::STM32::F4::SPI
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HAL::STM32::F4::DMA
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wizchip
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freertos_kernel
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nanomodbus
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)
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if (${TARGET_NAME} STREQUAL "modbus_rtu")
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target_compile_definitions(
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${TARGET_NAME} PRIVATE
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NMBS_RTU
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)
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elseif (${TARGET_NAME} STREQUAL "modbus_tcp")
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target_compile_definitions(
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${TARGET_NAME} PRIVATE
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NMBS_TCP
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)
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endif ()
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET_NAME}>
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)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${TARGET_NAME}> ${TARGET_NAME}.hex
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)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${TARGET_NAME}> ${TARGET_NAME}.bin
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)
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target_link_libraries(
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${TARGET_NAME}
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STM32::NoSys
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CMSIS::STM32::F401CC
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HAL::STM32::F4::CORTEX
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HAL::STM32::F4::RCC
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HAL::STM32::F4::PWR
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HAL::STM32::F4::GPIO
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HAL::STM32::F4::TIM
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HAL::STM32::F4::UART
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HAL::STM32::F4::USART
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HAL::STM32::F4::SPI
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HAL::STM32::F4::DMA
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wizchip
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freertos_kernel
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nanomodbus
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)
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endforeach()
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET_NAME}>
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)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${TARGET_NAME}> ${TARGET_NAME}.hex
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)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${TARGET_NAME}> ${TARGET_NAME}.bin
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)
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endforeach ()
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@ -11,27 +11,23 @@
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static void blink(void* args);
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static void modbus(void* args);
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uint32_t HAL_GetTick(void)
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{
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uint32_t HAL_GetTick(void) {
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return xTaskGetTickCount();
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}
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int main(void)
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{
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int main(void) {
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BSP_Init();
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xTaskCreate(blink, "blink", 128, NULL, 4, NULL);
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xTaskCreate(blink, "blink", 128, NULL, 4, NULL);
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xTaskCreate(modbus, "modbus", 128 * 16, NULL, 2, NULL);
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vTaskStartScheduler();
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for(;;){}
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for (;;) {}
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}
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static void blink(void* args)
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{
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for(;;)
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{
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static void blink(void* args) {
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for (;;) {
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HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_SET);
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vTaskDelay(500);
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HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
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@ -40,15 +36,19 @@ static void blink(void* args)
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}
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nmbs_t nmbs;
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nmbs_server_t nmbs_server =
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{
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.id = 0x01,
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.coils = {0,},
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.regs = {0,},
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nmbs_server_t nmbs_server = {
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.id = 0x01,
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.coils =
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{
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0,
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},
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.regs =
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{
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0,
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},
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};
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static void modbus(void* args)
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{
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static void modbus(void* args) {
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#if TEST_SERVER
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nmbs_server_init(&nmbs, &nmbs_server);
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#endif
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@ -59,7 +59,7 @@ static void modbus(void* args)
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nmbs_client_init(&nmbs);
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#endif
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for(;;){
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for (;;) {
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#if TEST_SERVER
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nmbs_server_poll(&nmbs);
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taskYIELD();
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@ -68,9 +68,8 @@ static void modbus(void* args)
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nmbs_set_destination_rtu_address(&nmbs, 0x01);
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nmbs_error status = nmbs_read_holding_registers(&nmbs, 0, 32, regs_test);
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status = nmbs_write_multiple_registers(&nmbs, 0, 32, regs_test);
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if(status != NMBS_ERROR_NONE)
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{
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while(true){}
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if (status != NMBS_ERROR_NONE) {
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while (true) {}
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}
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#endif
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}
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@ -1,85 +1,68 @@
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#include "blackpill/blackpill.h"
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#include "wizchip.h"
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#include <stdio.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include "FreeRTOS.h"
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#include "task.h"
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#include <socket.h>
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#include "nanomodbus.h"
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#include "nmbs/port.h"
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#include "task.h"
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#include <socket.h>
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extern SPI_HandleTypeDef hspi1;
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wiz_NetInfo net_info = {
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.mac = { 0xEA, 0x11, 0x22, 0x33, 0x44, 0xEA },
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.ip = {192, 168, 137, 100}, // You can find this ip if you set your ethernet port ip as 192.168.137.XXX
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.sn = {255, 255, 255, 0},
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.gw = {192, 168, 137, 1},
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.dns = {0, 0, 0, 0},
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}; // Network information.
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.mac = {0xEA, 0x11, 0x22, 0x33, 0x44, 0xEA},
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.ip = {192, 168, 137, 100}, // You can find this ip if you set your ethernet port ip as 192.168.137.XXX
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.sn = {255, 255, 255, 0},
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.gw = {192, 168, 137, 1},
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.dns = {0, 0, 0, 0},
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}; // Network information.
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uint8_t transaction_buf_sizes[] = {
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2, 2, 2, 2, 2, 2, 2, 2
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}; // All 2kB buffer setting for each sockets
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uint8_t transaction_buf_sizes[] = {2, 2, 2, 2, 2, 2, 2, 2}; // All 2kB buffer setting for each sockets
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#if USE_HAL_SPI_REGISTER_CALLBACKS == 0
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void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef* hspi) {
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wizchip_dma_rx_cplt((void*) hspi);
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}
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void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef* hspi) {
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wizchip_dma_tx_cplt((void*) hspi);
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}
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#endif
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uint32_t HAL_GetTick(void)
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{
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uint32_t HAL_GetTick(void) {
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return xTaskGetTickCount();
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}
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static void blink(void* args);
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static void modbus(void* args);
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int main(void)
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{
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int main(void) {
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BSP_Init();
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wizchip_register_hal(
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&hspi1,
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(fHalSpiTransaction) HAL_SPI_Receive,
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(fHalSpiTransaction) HAL_SPI_Transmit,
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(fHalSpiTransactionDma) HAL_SPI_Receive_DMA,
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(fHalSpiTransactionDma) HAL_SPI_Transmit_DMA,
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GPIOA,
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GPIO_PIN_15,
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(fHalGpioWritePin) HAL_GPIO_WritePin
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);
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wizchip_register_hal(&hspi1, (fHalSpiTransaction) HAL_SPI_Receive, (fHalSpiTransaction) HAL_SPI_Transmit,
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(fHalSpiTransactionDma) HAL_SPI_Receive_DMA, (fHalSpiTransactionDma) HAL_SPI_Transmit_DMA,
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GPIOA, GPIO_PIN_15, (fHalGpioWritePin) HAL_GPIO_WritePin);
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wizchip_init(transaction_buf_sizes, transaction_buf_sizes);
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setSHAR(net_info.mac);
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setSIPR(net_info.ip);
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setSUBR(net_info.sn);
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setGAR (net_info.gw);
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setGAR(net_info.gw);
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xTaskCreate(blink, "blink", 128, NULL, 4, NULL);
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xTaskCreate(modbus, "modbus", 128 * 16, NULL, 2, NULL);
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xTaskCreate(blink, "blink", 128, NULL, 4, NULL);
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xTaskCreate(modbus, "modbus", 128 * 16, NULL, 2, NULL);
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vTaskStartScheduler();
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while(true)
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{
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}
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while (true) {}
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}
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static void blink(void* args)
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{
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for(;;)
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{
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static void blink(void* args) {
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for (;;) {
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HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_SET);
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vTaskDelay(500);
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HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
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@ -88,41 +71,43 @@ static void blink(void* args)
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}
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static nmbs_t nmbs;
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static nmbs_server_t nmbs_server =
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{
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.id = 0x01,
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.coils = {0,},
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.regs = {0,},
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static nmbs_server_t nmbs_server = {
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.id = 0x01,
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.coils =
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{
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0,
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},
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.regs =
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{
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0,
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},
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};
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static void modbus(void* args)
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{
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static void modbus(void* args) {
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int status;
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nmbs_server_init(&nmbs, &nmbs_server);
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for(;;)
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{
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switch ((status = getSn_SR(MB_SOCKET)))
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{
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case SOCK_ESTABLISHED:
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nmbs_server_poll(&nmbs);
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break;
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case SOCK_INIT :
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listen(MB_SOCKET);
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break;
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case SOCK_CLOSED:
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socket(MB_SOCKET, Sn_MR_TCP, 502, 0);
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break;
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case SOCK_CLOSE_WAIT :
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disconnect(MB_SOCKET);
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break;
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for (;;) {
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switch ((status = getSn_SR(MB_SOCKET))) {
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case SOCK_ESTABLISHED:
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nmbs_server_poll(&nmbs);
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break;
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default:
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taskYIELD();
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break;
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case SOCK_INIT:
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listen(MB_SOCKET);
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break;
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case SOCK_CLOSED:
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socket(MB_SOCKET, Sn_MR_TCP, 502, 0);
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break;
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case SOCK_CLOSE_WAIT:
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disconnect(MB_SOCKET);
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break;
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default:
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taskYIELD();
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break;
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}
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}
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}
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@ -1,6 +1,6 @@
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#include <string.h>
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#include "nmbs/port.h"
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#include "FreeRTOS.h"
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#include <string.h>
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#ifdef NMBS_TCP
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static int32_t read_socket(uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg);
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@ -10,58 +10,60 @@ static int32_t write_socket(const uint8_t* buf, uint16_t count, int32_t byte_tim
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static int32_t read_serial(uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg);
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static int32_t write_serial(const uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg);
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#if MB_UART_DMA
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#if MB_UART_DMA
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#include "queue.h"
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xQueueHandle rtu_rx_q;
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uint8_t rtu_rx_b[MB_RX_BUF_SIZE];
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uint8_t rtu_rx_b[MB_RX_BUF_SIZE];
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#endif
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#endif
|
||||
|
||||
static nmbs_server_t* server;
|
||||
|
||||
static nmbs_error server_read_coils(uint16_t address, uint16_t quantity, nmbs_bitfield coils_out, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_read_holding_registers(uint16_t address, uint16_t quantity, uint16_t* registers_out, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_read_coils(uint16_t address, uint16_t quantity, nmbs_bitfield coils_out, uint8_t unit_id,
|
||||
void* arg);
|
||||
static nmbs_error server_read_holding_registers(uint16_t address, uint16_t quantity, uint16_t* registers_out,
|
||||
uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_single_coil(uint16_t address, bool value, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_multiple_coils(uint16_t address, uint16_t quantity, const nmbs_bitfield coils, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_multiple_coils(uint16_t address, uint16_t quantity, const nmbs_bitfield coils,
|
||||
uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_single_register(uint16_t address, uint16_t value, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_multiple_registers(uint16_t address, uint16_t quantity, const uint16_t* registers, uint8_t unit_id, void* arg);
|
||||
static nmbs_error server_write_multiple_registers(uint16_t address, uint16_t quantity, const uint16_t* registers,
|
||||
uint8_t unit_id, void* arg);
|
||||
|
||||
nmbs_error nmbs_server_init(nmbs_t* nmbs, nmbs_server_t* _server)
|
||||
{
|
||||
nmbs_error nmbs_server_init(nmbs_t* nmbs, nmbs_server_t* _server) {
|
||||
nmbs_platform_conf conf;
|
||||
nmbs_callbacks cb;
|
||||
nmbs_callbacks cb;
|
||||
|
||||
nmbs_platform_conf_create(&conf);
|
||||
#ifdef NMBS_TCP
|
||||
conf.transport = NMBS_TRANSPORT_TCP;
|
||||
conf.read = read_socket;
|
||||
conf.transport = NMBS_TRANSPORT_TCP;
|
||||
conf.read = read_socket;
|
||||
conf.write = write_socket;
|
||||
#endif
|
||||
#endif
|
||||
#ifdef NMBS_RTU
|
||||
conf.transport = NMBS_TRANSPORT_RTU;
|
||||
conf.read = read_serial;
|
||||
conf.transport = NMBS_TRANSPORT_RTU;
|
||||
conf.read = read_serial;
|
||||
conf.write = write_serial;
|
||||
#endif
|
||||
|
||||
server = _server;
|
||||
|
||||
nmbs_callbacks_create(&cb);
|
||||
cb.read_coils = server_read_coils;
|
||||
cb.read_holding_registers = server_read_holding_registers;
|
||||
cb.write_single_coil = server_write_single_coil;
|
||||
cb.write_multiple_coils = server_write_multiple_coils;
|
||||
cb.write_single_register = server_write_single_register;
|
||||
cb.write_multiple_registers = server_write_multiple_registers;
|
||||
cb.read_coils = server_read_coils;
|
||||
cb.read_holding_registers = server_read_holding_registers;
|
||||
cb.write_single_coil = server_write_single_coil;
|
||||
cb.write_multiple_coils = server_write_multiple_coils;
|
||||
cb.write_single_register = server_write_single_register;
|
||||
cb.write_multiple_registers = server_write_multiple_registers;
|
||||
|
||||
#if MB_UART_DMA
|
||||
#if MB_UART_DMA
|
||||
rtu_rx_q = xQueueCreate(MB_RX_BUF_SIZE, sizeof(uint8_t));
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(&MB_UART, rtu_rx_b, MB_RX_BUF_SIZE);
|
||||
#endif
|
||||
|
||||
nmbs_error status = nmbs_server_create(nmbs, server->id, &conf, &cb);
|
||||
if(status != NMBS_ERROR_NONE)
|
||||
{
|
||||
if (status != NMBS_ERROR_NONE) {
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -71,25 +73,23 @@ nmbs_error nmbs_server_init(nmbs_t* nmbs, nmbs_server_t* _server)
|
||||
return NMBS_ERROR_NONE;
|
||||
}
|
||||
|
||||
nmbs_error nmbs_client_init(nmbs_t* nmbs)
|
||||
{
|
||||
nmbs_error nmbs_client_init(nmbs_t* nmbs) {
|
||||
nmbs_platform_conf conf;
|
||||
|
||||
nmbs_platform_conf_create(&conf);
|
||||
#ifdef NMBS_TCP
|
||||
conf.transport = NMBS_TRANSPORT_TCP;
|
||||
conf.read = read_socket;
|
||||
conf.transport = NMBS_TRANSPORT_TCP;
|
||||
conf.read = read_socket;
|
||||
conf.write = write_socket;
|
||||
#endif
|
||||
#endif
|
||||
#ifdef NMBS_RTU
|
||||
conf.transport = NMBS_TRANSPORT_RTU;
|
||||
conf.read = read_serial;
|
||||
conf.transport = NMBS_TRANSPORT_RTU;
|
||||
conf.read = read_serial;
|
||||
conf.write = write_serial;
|
||||
#endif
|
||||
|
||||
nmbs_error status = nmbs_client_create(nmbs, &conf);
|
||||
if(status != NMBS_ERROR_NONE)
|
||||
{
|
||||
if (status != NMBS_ERROR_NONE) {
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -100,27 +100,21 @@ nmbs_error nmbs_client_init(nmbs_t* nmbs)
|
||||
}
|
||||
|
||||
|
||||
static nmbs_server_t* get_server(uint8_t id)
|
||||
{
|
||||
if(id == server->id)
|
||||
{
|
||||
static nmbs_server_t* get_server(uint8_t id) {
|
||||
if (id == server->id) {
|
||||
return server;
|
||||
}
|
||||
else
|
||||
{
|
||||
else {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static nmbs_error server_read_coils(uint16_t address, uint16_t quantity, nmbs_bitfield coils_out, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_read_coils(uint16_t address, uint16_t quantity, nmbs_bitfield coils_out, uint8_t unit_id,
|
||||
void* arg) {
|
||||
nmbs_server_t* server = get_server(unit_id);
|
||||
|
||||
for(size_t i = 0; i < quantity; i++)
|
||||
{
|
||||
if((address>>3) > COIL_BUF_SIZE)
|
||||
{
|
||||
for (size_t i = 0; i < quantity; i++) {
|
||||
if ((address >> 3) > COIL_BUF_SIZE) {
|
||||
return NMBS_ERROR_INVALID_REQUEST;
|
||||
}
|
||||
nmbs_bitfield_write(coils_out, address, nmbs_bitfield_read(server->coils, address));
|
||||
@ -129,14 +123,12 @@ static nmbs_error server_read_coils(uint16_t address, uint16_t quantity, nmbs_bi
|
||||
return NMBS_ERROR_NONE;
|
||||
}
|
||||
|
||||
static nmbs_error server_read_holding_registers(uint16_t address, uint16_t quantity, uint16_t* registers_out, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_read_holding_registers(uint16_t address, uint16_t quantity, uint16_t* registers_out,
|
||||
uint8_t unit_id, void* arg) {
|
||||
nmbs_server_t* server = get_server(unit_id);
|
||||
|
||||
for(size_t i = 0; i < quantity; i++)
|
||||
{
|
||||
if(address > REG_BUF_SIZE)
|
||||
{
|
||||
for (size_t i = 0; i < quantity; i++) {
|
||||
if (address > REG_BUF_SIZE) {
|
||||
return NMBS_ERROR_INVALID_REQUEST;
|
||||
}
|
||||
registers_out[i] = server->regs[address++];
|
||||
@ -144,24 +136,20 @@ static nmbs_error server_read_holding_registers(uint16_t address, uint16_t quant
|
||||
return NMBS_ERROR_NONE;
|
||||
}
|
||||
|
||||
static nmbs_error server_write_single_coil(uint16_t address, bool value, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_write_single_coil(uint16_t address, bool value, uint8_t unit_id, void* arg) {
|
||||
uint8_t coil = 0;
|
||||
if(value)
|
||||
{
|
||||
if (value) {
|
||||
coil |= 0x01;
|
||||
}
|
||||
return server_write_multiple_coils(address, 1, &coil, unit_id, arg);
|
||||
}
|
||||
|
||||
static nmbs_error server_write_multiple_coils(uint16_t address, uint16_t quantity, const nmbs_bitfield coils, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_write_multiple_coils(uint16_t address, uint16_t quantity, const nmbs_bitfield coils,
|
||||
uint8_t unit_id, void* arg) {
|
||||
nmbs_server_t* server = get_server(unit_id);
|
||||
|
||||
for(size_t i = 0; i < quantity; i++)
|
||||
{
|
||||
if((address>>3) > COIL_BUF_SIZE)
|
||||
{
|
||||
for (size_t i = 0; i < quantity; i++) {
|
||||
if ((address >> 3) > COIL_BUF_SIZE) {
|
||||
return NMBS_ERROR_INVALID_REQUEST;
|
||||
}
|
||||
nmbs_bitfield_write(server->coils, address, nmbs_bitfield_read(coils, i));
|
||||
@ -170,20 +158,17 @@ static nmbs_error server_write_multiple_coils(uint16_t address, uint16_t quantit
|
||||
return NMBS_ERROR_NONE;
|
||||
}
|
||||
|
||||
static nmbs_error server_write_single_register(uint16_t address, uint16_t value, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_write_single_register(uint16_t address, uint16_t value, uint8_t unit_id, void* arg) {
|
||||
uint16_t reg = value;
|
||||
return server_write_multiple_registers(address, 1, ®, unit_id, arg);
|
||||
}
|
||||
|
||||
static nmbs_error server_write_multiple_registers(uint16_t address, uint16_t quantity, const uint16_t* registers, uint8_t unit_id, void* arg)
|
||||
{
|
||||
static nmbs_error server_write_multiple_registers(uint16_t address, uint16_t quantity, const uint16_t* registers,
|
||||
uint8_t unit_id, void* arg) {
|
||||
nmbs_server_t* server = get_server(unit_id);
|
||||
|
||||
for(size_t i = 0; i < quantity; i++)
|
||||
{
|
||||
if(address > REG_BUF_SIZE)
|
||||
{
|
||||
for (size_t i = 0; i < quantity; i++) {
|
||||
if (address > REG_BUF_SIZE) {
|
||||
return NMBS_ERROR_INVALID_REQUEST;
|
||||
}
|
||||
server->regs[address++] = registers[i];
|
||||
@ -192,66 +177,53 @@ static nmbs_error server_write_multiple_registers(uint16_t address, uint16_t qua
|
||||
}
|
||||
|
||||
#ifdef NMBS_TCP
|
||||
int32_t read_socket(uint8_t *buf, uint16_t count, int32_t byte_timeout_ms, void *arg)
|
||||
{
|
||||
int32_t read_socket(uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg) {
|
||||
uint32_t tick_start = HAL_GetTick();
|
||||
while(recv(MB_SOCKET, buf, count) != count)
|
||||
{
|
||||
if(HAL_GetTick() - tick_start >= (uint32_t)byte_timeout_ms)
|
||||
{
|
||||
while (recv(MB_SOCKET, buf, count) != count) {
|
||||
if (HAL_GetTick() - tick_start >= (uint32_t) byte_timeout_ms) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
int32_t write_socket(const uint8_t *buf, uint16_t count, int32_t byte_timeout_ms, void *arg)
|
||||
{
|
||||
int32_t write_socket(const uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg) {
|
||||
return send(MB_SOCKET, buf, count);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef NMBS_RTU
|
||||
static int32_t read_serial(uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg)
|
||||
{
|
||||
static int32_t read_serial(uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg) {
|
||||
#if MB_UART_DMA
|
||||
uint32_t tick_start = HAL_GetTick();
|
||||
while(uxQueueMessagesWaiting(rtu_rx_q) < count)
|
||||
{
|
||||
if(HAL_GetTick() - tick_start >= (uint32_t)byte_timeout_ms)
|
||||
{
|
||||
while (uxQueueMessagesWaiting(rtu_rx_q) < count) {
|
||||
if (HAL_GetTick() - tick_start >= (uint32_t) byte_timeout_ms) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
for(int i = 0; i < count; i++)
|
||||
{
|
||||
for (int i = 0; i < count; i++) {
|
||||
xQueueReceive(rtu_rx_q, buf + i, 1);
|
||||
}
|
||||
return count;
|
||||
#else
|
||||
HAL_StatusTypeDef status = HAL_UART_Receive(&MB_UART, buf, count, byte_timeout_ms);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if (status == HAL_OK) {
|
||||
return count;
|
||||
}
|
||||
else
|
||||
{
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
static int32_t write_serial(const uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg)
|
||||
{
|
||||
#if MB_UART_DMA
|
||||
static int32_t write_serial(const uint8_t* buf, uint16_t count, int32_t byte_timeout_ms, void* arg) {
|
||||
#if MB_UART_DMA
|
||||
HAL_UART_Transmit_DMA(&MB_UART, buf, count);
|
||||
#else
|
||||
HAL_StatusTypeDef status = HAL_UART_Transmit(&MB_UART, buf, count, byte_timeout_ms);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if (status == HAL_OK) {
|
||||
return count;
|
||||
}
|
||||
else
|
||||
{
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -259,16 +231,13 @@ static int32_t write_serial(const uint8_t* buf, uint16_t count, int32_t byte_tim
|
||||
|
||||
|
||||
#if MB_UART_DMA
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
||||
{
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef* huart, uint16_t Size) {
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
if(huart == &MB_UART)
|
||||
{
|
||||
for(int i = 0; i < Size; i++)
|
||||
{
|
||||
if (huart == &MB_UART) {
|
||||
for (int i = 0; i < Size; i++) {
|
||||
xQueueSendFromISR(rtu_rx_q, rtu_rx_b + i, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(huart, rtu_rx_b, MB_RX_BUF_SIZE);
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(huart, rtu_rx_b, MB_RX_BUF_SIZE);
|
||||
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
||||
}
|
||||
// You may add your additional uart handler below
|
||||
|
||||
@ -6,32 +6,32 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
// Max size of coil and register area
|
||||
#define COIL_BUF_SIZE 1024
|
||||
#define REG_BUF_SIZE 2048
|
||||
#define COIL_BUF_SIZE 1024
|
||||
#define REG_BUF_SIZE 2048
|
||||
|
||||
// NanoModbus include
|
||||
#include "nanomodbus.h"
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
#ifdef NMBS_TCP
|
||||
// modbus tcp
|
||||
// modbus tcp
|
||||
#define MB_SOCKET 1
|
||||
#include <socket.h>
|
||||
#endif
|
||||
|
||||
#ifdef NMBS_RTU
|
||||
// modbus rtu
|
||||
#define MB_UART huart1
|
||||
#define MB_UART_DMA 1
|
||||
#define MB_RX_BUF_SIZE 256
|
||||
#define MB_UART huart1
|
||||
#define MB_UART_DMA 1
|
||||
#define MB_RX_BUF_SIZE 256
|
||||
extern UART_HandleTypeDef MB_UART;
|
||||
#endif
|
||||
|
||||
typedef struct tNmbsServer{
|
||||
uint8_t id;
|
||||
uint8_t coils[COIL_BUF_SIZE];
|
||||
typedef struct tNmbsServer {
|
||||
uint8_t id;
|
||||
uint8_t coils[COIL_BUF_SIZE];
|
||||
uint16_t regs[REG_BUF_SIZE];
|
||||
}nmbs_server_t;
|
||||
} nmbs_server_t;
|
||||
|
||||
nmbs_error nmbs_server_init(nmbs_t* nmbs, nmbs_server_t* server);
|
||||
nmbs_error nmbs_client_init(nmbs_t* nmbs);
|
||||
|
||||
@ -1,29 +1,37 @@
|
||||
# STM32 nanomodbus porting
|
||||
# STM32 nanomodbus porting
|
||||
|
||||
## Target hardware
|
||||
|
||||
|
||||
|
||||
- Blackpill board
|
||||
- STM32F401CCUx
|
||||
- STM32F401CCUx
|
||||
- USART1 (with/without) DMA
|
||||
- PA9 : TX1
|
||||
- PA10 : RX1
|
||||
- PA9 : TX1
|
||||
- PA10 : RX1
|
||||
- SPI1 with DMA (connected to W5500)
|
||||
- PB3 : SCK1
|
||||
- PB4 : MISO1
|
||||
- PB5 : MOSI1
|
||||
- PA15 : NSS (Software select)
|
||||
- PB3 : SCK1
|
||||
- PB4 : MISO1
|
||||
- PB5 : MOSI1
|
||||
- PA15 : NSS (Software select)
|
||||
|
||||
## Toolchain and environment
|
||||
|
||||
Tested on Mac OS Sonoma(Apple Silicon) & Windows 10 but other os having same toolchain should have no problem.
|
||||
|
||||
- arm-none-eabi-gcc
|
||||
- arm-none-eabi-gcc
|
||||
- cmake
|
||||
- ninja
|
||||
- openocd
|
||||
- vscode
|
||||
- CMake
|
||||
- cortex-debug
|
||||
- CMake
|
||||
- cortex-debug
|
||||
|
||||
## Building
|
||||
|
||||
```
|
||||
mkdir build
|
||||
cd build
|
||||
cmake ..
|
||||
make -j16
|
||||
```
|
||||
|
||||
Loading…
Reference in New Issue
Block a user